The present invention relates to a memory system using a flash memory having a restriction on the number of reads and a control method thereof.
In recent years, a semiconductor memory is being used throughout from a main storage of a large-scale computer to a personal computer, a home electric appliance, a mobile phone, and the like. In particular, a flash EEPROM type nonvolatile memory (hereinafter, referred to as “flash memory”) is attracting a lot of attention. There are advantages in that the flash memory retains data even when power is off and has a structure suitable for high integration. For this reason, the flash memory is being used in many information devices such as a mobile phone, a digital camera, and the like.
The flash memory is mainly a NOR type and a NAND type. In the NOR type, data is readable at a high rate and the number of reads is approximately 1013. The NOR type is used as an instruction code storage of a portable device. On the other hand, the NOR type has a small effective bandwidth at the time of writing data and is not suitable for a large capacity of file record or the like. Compared with this, the NAND type is advantageous in that a high integration is facilitated and an effective burst bandwidth is high since a so-called burst read (in which data is continuously read for a row of addresses at a high rate) is possible. Moreover, there is an advantage in that data is fetched in a burst mode and a large number of bits are collectively writable in a page unit since the number of bits writable to or erasable from a memory cell at the same time is large. Consequently, an execution bandwidth can increase, such that it is available in a memory card, a USB memory, a memory of a mobile phone, and the like and is recently being considered as a replacement of the hard disk.
On the other hand, there are a restriction on the number of writes/erases and a restriction on the number of reads as one obstacle when the NAND type flash memory is considered as the replacement of the hard disk.
In the write/erase operation of the flash memory, a high voltage is applied to a gate for a substrate and electrons are injected into a floating gate. For this reason, the write/erase operation is executed a number of times and an oxide film around the floating gate is deteriorated, such that data is destroyed. The number of writes for the flash memory is approximately 105, and is smaller than those of other nonvolatile memories. When the flash memory is used as the hard disk, there is a problem in that data may be destroyed due to a restriction on the number of writes/erases and the system may be obstructed. As a countermeasure to this, wear leveling for averaging the number of writes/erases is performed by counting the number of erases on a block basis, setting a threshold value, and converting physical addresses of a block of the small number of erases and a block of the large number of erases.
In the read of the NAND type flash memory, 0 V is applied to a gate of a selection cell for each bit line, a high voltage (V Read) is applied to a gate of a non-selection cell and a selection gate, and “1” or “0” is determined according to whether the selection cell is conductive. Consequently, when the read is repeated, the high voltage is repeatedly applied to non-selection cells (corresponding to all memory cells of all pages except a read target as viewed from a block unit), electrons enters the floating gate while passing through the oxide film, and a threshold value of the memory cell is varied, thereby leading to data destruction (so-called read disturb). Moreover, the use time (or the number of accesses) increases, such that the oxide film is further deteriorated due to the write/erase operation and a frequency of occurrence of the read disturb becomes high. A limit of the number of reads of the NAND type flash memory is approximately 104. To prevent this read disturb, a block of the large number of reads should be appropriately rewritten and the threshold value should return (or be refreshed) to the original state (for example, see JP-A-2004-326867).
However, in a conventional memory system and a conventional control method thereof, a counter of the number of reads is provided in a page unit. When the number of reads reaches a reference value, data passes through an error correction circuit (ECC). When the number of reads exceeds the reference number, a target block is rewritten and refreshed. For this reason, various problems may occur according to degrees of error correction capability of the ECC. That is, when the correction capability is low, an error of several bits may be only detected in a unit of one page at the most. There is a problem in that a countermeasure may not be taken when read disturb occurs in several tens˜several hundreds bits at one time. When the error correction capability is high, there is a problem in that a ratio of redundant bits to data is large and a ratio at which ECC bits occupy a memory capacity is large or there is a problem in that a data transmission time is delayed since an error correction is time-consuming. Moreover, there is a problem in that an overhead of a chip area increases since a complex ECC circuit should be inserted into the system.
The NAND type flash memory develops into a multivalued structure for storing information of two or more bits in one cell and is in a direction in which a threshold value is strictly controlled. For this reason, it may be considered that the effect of read disturb is a more serious problem in the future.